VHDL运算单元与测试平台仿真运行时间为0秒问题求助

现有VHDL程序包含两个源文件：8bit_PU.vhd（实体bit_PU）和8bit_Tb.vhd。程序预期读取3位操作码至operation端口，解码后对随时间变化的8位std_logic_vector类型操作数operand1和operand2执行运算，结果输出至8位std_logic_vector类型result端口，目前仅实现加法操作。

源文件代码 #

8bit_PU.vhd #

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity bit_PU is
    port(operation : in std_logic_vector (2 downto 0); 
         Clk       : in std_logic;
         operand1  : in std_logic_vector (7 downto 0); 
         operand2  : in std_logic_vector (7 downto 0); 
         result    : out std_logic_vector(7 downto 0)
         );  
end bit_PU;
 
architecture proc of bit_PU is
        function Add (op1 : std_logic_vector (7 downto 0); 
                      op2 : std_logic_vector (7 downto 0)) return std_logic_vector is
        variable res: std_logic_vector (7 downto 0);  
        begin
            res := std_logic_vector((unsigned(op1)+unsigned(op2)) mod 256);
            return res;
        end function;
 
begin
 
    process(Clk) is
    begin
        if rising_edge(Clk) then
                result <= Add(operand1, operand2);
        end if; 
    end process;
 
end architecture;

8bit_Tb.vhd #

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
   
entity bit_Tb is
end bit_Tb;
   
architecture proc of bit_Tb is
   
        component bit_PU is
            port(operation : in std_logic_vector (2 downto 0);
                 Clk       : in std_logic;
                 operand1  : in std_logic_vector (7 downto 0);
                 operand2  : in std_logic_vector (7 downto 0);
                 result    : out std_logic_vector(7 downto 0)
                 );
        end component bit_PU;
 
signal   Clk  : std_logic  := '0';
constant Freq : integer    := 100;
constant PeriodTime : time := 1000 ms / Freq;
signal   operation  : std_logic_vector (2 downto 0) := "000";
signal   result     : std_logic_vector (7 downto 0);
signal   operand1   : std_logic_vector (7 downto 0) := (others => '0');
signal   operand2   : std_logic_vector (7 downto 0) := (others => '0');
begin                                                                                                                                                                                                                                         
   
    i_bit_PU: component bit_PU
    port map(Clk => Clk,
     operation => operation,
     operand1  => operand1,
     operand2  => operand2,
     result    => result);
   
    Clk <= not Clk after PeriodTime / 2;
   
    process (Clk) is
    begin
        if rising_edge(Clk) then
            if unsigned(operand1) < unsigned(operand2) or (operand1 = x"FF" and operand2 = x"00") then
                operand1 <= std_logic_vector((unsigned(operand1)+1) mod 256);
            else
                operand2 <= std_logic_vector((unsigned(operand2)+1) mod 256);
            end if; 
        end if; 
end process;
   
end architecture;

当前编译与执行步骤 #

$ ghdl -s 8bit_PU.vhd
$ ghdl -s 8bit_Tb.vhd
$ ghdl -a 8bit_PU.vhd
$ ghdl -a 8bit_Tb.vhd
$ ghdl -e bit_PU
$ ghdl -r bit_PU --vcd=2nd_circuit.vcd

执行结果 #

$ gtkwave 2nd_circuit.vcd

GTKWave Analyzer v3.3.118 (w)1999-2023 BSI

[0] start time.
[0] end time.

仿真时长为0秒，单独测试两个文件（在8bit_PU.vhd中嵌入仿真测试平台、仅运行测试平台）均正常，曾尝试用work库显式例化DUT：

---
architecture proc of bit_Tb is
 signal   Clk  : std_logic  := '0';
 constant Freq : integer    := 100;
 constant PeriodTime : time := 1000 ms / Freq;
 signal   operation  : std_logic_vector (2 downto 0) := "000";
 signal   result     : std_logic_vector (7 downto 0);
 signal   operand1   : std_logic_vector (7 downto 0) := (others => '0');
 signal   operand2   : std_logic_vector (7 downto 0) := (others => '0');
 begin
      
      i_bit_PU: entity work.bit_PU(proc) -- 修改此处
      port map(Clk => Clk,
       operation => operation,
       operand1  => operand1,
       operand2  => operand2,
       result    => result);
---

但问题仍未解决。

问题根源与解决方法 #

问题核心 #

你当前运行的是DUT实体bit_PU，而非测试平台bit_Tb。DUT本身没有时间推进的逻辑，仿真会立即结束，导致VCD文件时长为0。

正确操作步骤 #

1. 编译后生成并运行测试平台实体：

# 重新编译（若已编译可跳过）
ghdl -a 8bit_PU.vhd
ghdl -a 8bit_Tb.vhd
# 生成测试平台可执行文件
ghdl -e bit_Tb
# 运行测试平台并生成VCD文件
ghdl -r bit_Tb --vcd=2nd_circuit.vcd
# 打开波形文件
gtkwave 2nd_circuit.vcd

2. 可选：指定仿真时长避免无限循环：

ghdl -r bit_Tb --vcd=2nd_circuit.vcd --stop-time=10ms

额外优化建议 #

• 在测试平台中添加断言语句自动验证结果：

process(Clk)
begin
    if rising_edge(Clk) then
        assert result = std_logic_vector((unsigned(operand1)+unsigned(operand2)) mod 256)
        report "加法结果错误" severity error;
    end if;
end process;

• 实体命名建议更清晰，比如将bit_PU改为EightBitPU，避免歧义。

内容的提问来源于stack exchange，提问作者DEADBEEF