Vivado Block RAM IP在两款Testbench中出现仿真矛盾求助

RAM配置 #

生成的RAM为16x255真双端口RAM（Port A和Port B），采用原生接口，两个端口均启用原语输出寄存器和RST信号，工作模式保持默认配置，端口配置和IP摘要分别见图1、图2。

Testbench A（手动信号配置） #

该测试平台通过手动方式配置所有控制信号、输入数据及I/O地址，代码如下：

module tb_blk_mem_1();
    reg rst, clk, clkb;
    reg blk_mem_wen, blk_mem_ren;
    wire wrst_busy, rrst_busy;
    reg [7:0] waddr_0, raddr_0;
    reg [15:0] din_0;
    wire [15:0] dout_0;
    reg ena;
    
    always begin
        #10 clk = ~clk;
    end
    
    always begin
        #10 clkb = ~clkb;
    end 
    
    initial begin
        clk = 1; rst = 1; blk_mem_wen = 0; blk_mem_ren = 0; waddr_0 = 255; raddr_0 = 3; din_0 = 65535;clkb = 1; ena = 1;
        #40 rst = 0;
        #180 blk_mem_wen = 1; 
        #20 din_0 = 1; waddr_0 = 0;
        #20 blk_mem_wen = 1; waddr_0 = 1; din_0 = 2;
        #20 blk_mem_wen = 1; waddr_0 = 2; din_0 = 3;
        #20 blk_mem_wen = 1; waddr_0 = 3; din_0 = 4;
        #20 blk_mem_wen = 0;ena = 0;
        #200 blk_mem_ren = 1; raddr_0 = 0;
        #20 blk_mem_ren = 1; raddr_0 = 1;
        #20 blk_mem_ren = 1; raddr_0 = 2;
        #20 blk_mem_ren = 1; raddr_0 = 3;
        #20 raddr_0 = 0;
        #20 raddr_0 = 1;

    end
    
    blk_mem_gen_1 blk_mem_gen_1(
        .clka(clk),
        .wea(blk_mem_wen),
        .addra(waddr_0),
        .dina(din_0),
        .douta(),
        .ena(ena),
        .addrb(raddr_0),
        .dinb(),
        .rsta(rst),
        .doutb(dout_0),
        .rstb(rst),
        .enb(blk_mem_ren),
        .web(1'b0),
        .clkb(clkb),
        .rsta_busy(wrst_busy),
        .rstb_busy(rrst_busy)
    );

endmodule

根据修正后的图3（MfLCy.png）仿真结果，Block RAM首次输入地址时无数据返回，且后续数据返回仅延迟1个时钟周期，与预期的2个周期不符。

Testbench B（自动信号生成） #

该测试平台通过自动累加方式生成地址和数据，代码如下：

module tb_blk_mem();
    wire [15:0] douta, doutb;
    reg clka, clkb;
    reg ena, enb;
    reg wea;
    reg rst;
    wire rsta_busy, rstb_busy;


    wire [15:0] dina;
    wire [7:0] addra, addrb;

    blk_mem_wr blk_mem_wr(
        .wr_clk(clka),
        .rst_busy(rsta_busy),
        .wr_data(dina),
        .wr_addr(addra),
        .wen(wea)
    );

    blk_mem_rd blk_mem_rd(
        .rd_clk(clkb),
        .ren(enb),
        .rst_busy(rstb_busy),
        .rd_addr(addrb)
    );


    blk_mem_gen_1 blk_mem_gen_1(
        .addra(addra),
        .addrb(addrb),
        .dina(dina),
        .dinb(),
        .clka(clka),
        .clkb(clkb),
        .ena(ena),
        .enb(enb),
        .wea(wea),
        .web(),
        .rsta(rst),
        .rstb(rst),
        .douta(),
        .doutb(doutb),
        .rsta_busy(rsta_busy),
        .rstb_busy(rstb_busy)
    );

    always begin
        #10 clka = !clka;
    end
    
    always begin
        #10 clkb = !clkb;
    end
    
    initial begin
        clka = 1; clkb = 1;rst = 1;ena = 1; enb = 0; wea = 0;
        #10 rst = 0; 
        #300 ena = 1'b1; wea = 1'b1;
        #400 wea = 1'b0;ena = 1'b0;
        #50 enb = 1;


        #400 $finish;
    end
endmodule

根据图4的仿真结果，Block RAM工作完全正常，超出地址范围的"X"属于正常现象。

疑问与求助 #

两款Testbench控制逻辑相近，但一款仿真异常、一款正常，更换Block RAM IP后问题仍存在，怀疑Testbench存在未发现的错误，寻求排查方向。

内容的提问来源于stack exchange，提问作者James Butler