如何为Verilog电路创建Testbench实现Modelsim自动仿真？

你的testbench无法工作核心是两个错误：

• 实例化了错误模块：你在testbench里调用的是testbench自身，而非要测试的circuit模块
• 端口大小写不匹配：circuit的端口是大写A/B/C/D/F，但你用小写.a/.b/.c/.d/.f映射，Verilog对标识符大小写敏感，会导致端口连接失败

修正后的基础版Testbench #

module testbench;
    reg A, B, C, D;
    wire F;
    
    // 正确实例化circuit模块，端口名严格匹配
    circuit TEST (
            .A(A),
            .B(B),
            .C(C),
            .D(D),
            .F(F)
        );

    initial begin
        // 遍历所有16种输入组合
        A = 0; B = 0; C = 0; D = 0; #10;   
        A = 0; B = 0; C = 0; D = 1; #10;        
        A = 0; B = 0; C = 1; D = 0; #10;
        A = 0; B = 0; C = 1; D = 1; #10;

        A = 0; B = 1; C = 0; D = 0; #10;
        A = 0; B = 1; C = 0; D = 1; #10;
        A = 0; B = 1; C = 1; D = 0; #10;
        A = 0; B = 1; C = 1; D = 1; #10;

        A = 1; B = 0; C = 0; D = 0; #10;
        A = 1; B = 0; C = 0; D = 1; #10;
        A = 1; B = 0; C = 1; D = 0; #10;
        A = 1; B = 0; C = 1; D = 1; #10;

        A = 1; B = 1; C = 0; D = 0; #10;
        A = 1; B = 1; C = 0; D = 1; #10;
        A = 1; B = 1; C = 1; D = 0; #10;
        A = 1; B = 1; C = 1; D = 1; #10;
        
        $finish;
    end

endmodule

更简洁的自动遍历版Testbench #

不用手动写16行输入，用循环自动生成所有组合，代码更易维护：

module testbench;
    reg [3:0] inputs; // 打包A/B/C/D，inputs[3]=A, inputs[2]=B, inputs[1]=C, inputs[0]=D
    wire F;
    
    circuit TEST (
            .A(inputs[3]),
            .B(inputs[2]),
            .C(inputs[1]),
            .D(inputs[0]),
            .F(F)
        );

    initial begin
        inputs = 4'b0000;
        // 循环遍历0到15（对应16种输入组合）
        repeat(16) begin
            #10;
            inputs = inputs + 1'b1;
        end
        $finish;
    end

    // 可选：导出波形文件，方便Modelsim查看
    initial begin
        $dumpfile("circuit_wave.vcd");
        $dumpvars(0, testbench);
    end
endmodule

Modelsim仿真步骤 #

1. 将circuit.v和修正后的testbench.v添加到工程
2. 编译两个文件
3. 启动仿真，选择testbench作为顶层模块
4. 添加信号到波形窗口，运行仿真即可查看所有输入组合对应的输出波形

内容的提问来源于stack exchange，提问作者Pascal