如何修改gem5中RVV向量长度？配置遇AttributeError错误求助

问题描述 #

我正在使用RVV intrinsics在gem5中模拟RISCV处理器上的算法，希望探究RVV向量长度（VLEN）对性能的影响。观察到gem5的RiscvISA.py文件中向量长度可配置，但在自定义仿真配置文件中尝试设置system.cpu.isa.vlen = xxx时，出现错误：AttributeError: Not allowed to set vlen on 'VectorParamValue'。

仿真配置文件如下：

import m5
from m5.objects import System, SrcClockDomain, VoltageDomain, Root
from m5.objects import RiscvO3CPU, Cache, AddrRange, SEWorkload, Process
from m5.objects import MemCtrl, DDR3_1600_8x8, SystemXBar, L2XBar


class L1Cache(Cache):
    assoc = 2
    tag_latency = 2
    data_latency = 2
    response_latency = 2
    mshrs = 4
    tgts_per_mshr = 20

    def connectCPU(self, cpu):
        raise NotImplementedError

    def connectBus(self, bus):
        self.mem_side = bus.cpu_side_ports


class L1ICache(L1Cache):
    size = '16kB'

    def connectCPU(self, cpu):
        self.cpu_side = cpu.icache_port


class L1DCache(L1Cache):
    size = '64kB'

    def connectCPU(self, cpu):
        self.cpu_side = cpu.dcache_port


class L2Cache(Cache):
    size = '256kB'
    assoc = 8
    tag_latency = 20
    data_latency = 20
    response_latency = 20
    mshrs = 20
    tgts_per_mshr = 12

    def connectCPUSideBus(self, bus):
        self.cpu_side = bus.mem_side_ports

    def connectMemSideBus(self, bus):
        self.mem_side = bus.cpu_side_ports


system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]

system.cpu = RiscvO3CPU()

# Create the L1 caches
system.cpu.icache = L1ICache()
system.cpu.dcache = L1DCache()

# Connect the caches to the CPU
system.cpu.icache.connectCPU(system.cpu)
system.cpu.dcache.connectCPU(system.cpu)

# Connect the CPU to the L2 bus
system.l2bus = L2XBar()

# Connect the L1 caches to the L2 bus
system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)

# Connect the L2 cache to the CPU side bus
system.l2cache = L2Cache()
system.l2cache.connectCPUSideBus(system.l2bus)

# Connect the L2 cache to the memory bus
system.membus = SystemXBar()
system.l2cache.connectMemSideBus(system.membus)

# Connect the CPU to the memory bus
system.cpu.createInterruptController()

system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.mem_side_ports

binary = './dct2d_riscv.out'

system.workload = SEWorkload.init_compatible(binary)

process = Process()
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()

# Run SE mode
root = Root(full_system=False, system=system)
m5.instantiate()

print("Beginning simulation!")
exit_event = m5.simulate()

print('Exiting @ tick {} because {}'
      .format(m5.curTick(), exit_event.getCause()))

解决方案 #

gem5中RVV的VLEN属于ISA的参数化配置项，不能在CPU对象实例化后直接修改isa.vlen，需通过以下两种方式设置：

方法1：实例化CPU时指定VLEN #

创建RiscvO3CPU对象时，直接传入isa的配置参数，示例如下：

# 导入RiscvISA配置类
from m5.objects import RiscvISA

# 实例化CPU时指定VLEN（例如设置为1024）
system.cpu = RiscvO3CPU(isa=RiscvISA(vlen=1024))

方法2：修改全局ISA默认配置（不推荐） #

若需要全局统一设置VLEN，可在配置文件开头修改RiscvISA的默认参数：

from m5.objects import RiscvISA
RiscvISA.vlen = 1024

# 后续再实例化CPU
system.cpu = RiscvO3CPU()

注意事项 #

1. VLEN的取值必须是64的倍数，符合RVV架构规范（如64、128、256、512、1024等）。
2. 编译测试程序时，需使用支持对应VLEN的RISCV工具链，确保RVV intrinsics的编译与仿真的VLEN匹配，避免兼容问题。
3. 部分旧版本gem5可能需要修改src/arch/riscv/RiscvISA.py中的默认VLEN后重新编译，但优先推荐上述配置文件动态指定的方式，无需重新编译。

内容的提问来源于stack exchange，提问作者Hugo Mårdbrink