Kintex 7 KC705 FPGA板LCD引脚输出TTL信号DRC错误求助
我使用Kintex7 KC705 FPGA板生成3路TTL信号以控制RF开关，计划从板载LCD引脚J31（共14引脚，13脚为GND、14脚为5V VCC）输出这三路信号。编写的约束文件（对应信号为ctrl_1、ctrl_2、ctrl_3）如下：
set_property PACKAGE_PIN Y10 [get_ports {ctrl_1[0]}] #1 on LCD PORTS set_property IOSTANDARD LVCMOS15 [get_ports {ctrl_1[0]}] set_property PACKAGE_PIN AA10 [get_ports {ctrl_2[0]}] #3 on LCD PORTS set_property IOSTANDARD LVCMOS15 [get_ports {ctrl_2[0]}] set_property PACKAGE_PIN AB10 [get_ports {ctrl_3[0]}] #9 on LCD PORTS set_property IOSTANDARD LVCMOS15 [get_ports {ctrl_3[0]}] ############################ DEBUG D'UNE ERREUR ###################################### ####################################################################################3 set_property SEVERITY {warning}[get_drc_checks NSTD-1] set_property SEVERITY {warning}[get_drc_checks UCIO-1]
生成比特流时出现以下DRC错误：
[DRC NSTD-1] Unspecified I/O Standard: 3 out of 18 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ctrl_1, ctrl_2, and ctrl_3.
[DRC UCIO-1] Unconstrained Logical Port: 3 out of 18 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ctrl_1, ctrl_2, and ctrl_3.
我尝试将IOSTANDARD从LVCMOS15改为LVCMOS18、25、33，但问题仍未解决。程序的实体部分代码如下：
entity gtwizard_0_exdes is generic ( EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 1; EXAMPLE_LANE_WITH_START_CHAR : integer := 0; -- specifies lane with unique start frame ch EXAMPLE_WORDS_IN_BRAM : integer := 512; -- specifies amount of data in BRAM EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model STABLE_CLOCK_PERIOD : integer := 16; EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets); port( Q0_CLK1_GTREFCLK_PAD_N_IN : in std_logic; Q0_CLK1_GTREFCLK_PAD_P_IN : in std_logic; Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic; Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic; DRP_CLK_IN_P : in std_logic; DRP_CLK_IN_N : in std_logic; RXN_IN : in std_logic_vector(1 downto 0); RXP_IN : in std_logic_vector(1 downto 0); TXN_OUT : out std_logic_vector(1 downto 0); TXP_OUT : out std_logic_vector(1 downto 0); clk_out1 : out std_logic; ctrl_1 : out std_logic ; ctrl_2 : out std_logic ; ctrl_3 : out std_logic );
问题根源与解决方案
1. 约束端口不匹配
实体代码中ctrl_1、ctrl_2、ctrl_3是单比特std_logic信号，但约束文件里错误使用了数组索引ctrl_1[0]格式，导致Vivado无法识别约束与端口的对应关系，进而判定这些端口未分配IO标准和引脚位置。
2. 修正约束文件
修改约束文件中的端口名，去掉数组索引，并修复SEVERITY命令的语法错误（原命令中{warning}与[get_drc_checks...]之间缺少空格，导致命令失效）：
set_property PACKAGE_PIN Y10 [get_ports {ctrl_1}] #1 on LCD PORTS set_property IOSTANDARD LVCMOS15 [get_ports {ctrl_1}] set_property PACKAGE_PIN AA10 [get_ports {ctrl_2}] #3 on LCD PORTS set_property IOSTANDARD LVCMOS15 [get_ports {ctrl_2}] set_property PACKAGE_PIN AB10 [get_ports {ctrl_3}] #9 on LCD PORTS set_property IOSTANDARD LVCMOS15 [get_ports {ctrl_3}] set_property SEVERITY {warning} [get_drc_checks NSTD-1] set_property SEVERITY {warning} [get_drc_checks UCIO-1]
3. 确认IO标准匹配性
KC705的J31引脚所属IO Bank的电压需与IOSTANDARD对应，LCD接口通常采用3.3V电平，建议查阅KC705官方手册确认J31所在Bank的电压，若为3.3V则将IOSTANDARD改为LVCMOS33。
4. 重新执行流程
修正约束后，重新运行综合、实现步骤，再尝试生成比特流即可解决DRC错误。
内容的提问来源于stack exchange，提问作者chaima chabbat
