Verilog状态机在Vivado编译报错求助（Basys3开发板）

刚接触Verilog，在使用Vivado为Basys3开发板编写代码时持续出现报错，尝试将错误改为警告后问题仍未解决，恳请协助排查问题。

Verilog代码 #

module StateMachine(
output reg[2:0] state, input x, clk, output led0,led1,led2);
 wire sysHardwareClock,scaledClock; 
 parameter S0 = 3'b000, S1 = 3'b001, S2 = 2'b010, S3 = 2'b011, S4 = 2'b100, S5= 3'b101;
 slowClock(sysHardwareClock,scaledClock);
 always @ (posedge scaledClock)
  begin
     case (state)
       S0:state<= S1;
       S1:state<= S2;
       S2:state<= S3;
       S3:state<= S4;
       S4:state<= S5;
       endcase
   end
endmodule


module slowClock(clk, slowclk);
input clk;
output slowclk;

reg slowclk = 1'b0;
reg [27:0] counter;

always@(posedge clk)
  begin
    counter <= counter + 1;
    if ( counter == 25000000)
        begin
          counter <= 0;
         slowclk <= ~slowclk;
    end
  end
endmodule  

约束文件 #

## Clock signal
set_property PACKAGE_PIN W5 [get_ports sysHardwareClock]                            
    set_property IOSTANDARD LVCMOS33 [get_ports sysHardwareClock]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports sysHardwareClock]

## LEDs
set_property PACKAGE_PIN U16 [get_ports state[0]]                   
    set_property IOSTANDARD LVCMOS33 [get_ports state[0]]
set_property PACKAGE_PIN E19 [get_ports state[0]]                   
    set_property IOSTANDARD LVCMOS33 [get_ports state[2]]
set_property PACKAGE_PIN U19 [get_ports state[3]]                   
    set_property IOSTANDARD LVCMOS33 [get_ports state[3]]

内容的提问来源于stack exchange，提问作者owen krumm