如何为VHDL Generate语句内的实例编写嵌入式配置？

在VHDL架构声明区域中，我会使用类似for and_gate_inst : and_gate use entity work.and_gate(rtl);的嵌入式配置，但当实例位于Generate语句内部时，之前的写法报错，不清楚正确的编写方式。

以下是我报错的示例代码：

library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
    port (
        inp1_i, inp2_i : in std_logic;
        out_o  : out std_logic
    );
end entity;
architecture rtl of and_gate is
begin
    out_o <= inp1_i and inp2_i;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
entity embedded_conf is
end entity embedded_conf;
library work;
architecture struct of embedded_conf is
    signal inp1, inp2, out1  : std_logic;
    component and_gate is
        port (
            inp1_i : in  std_logic;
            inp2_i : in  std_logic;
            out_o  : out std_logic
        );
    end component;
    for dummy_g for and_gate_inst : and_gate use entity work.and_gate(rtl); -- 写法错误!!!
begin
    dummy_g: if true generate
        and_gate_inst : and_gate
            port map (
                inp1_i => inp1,
                inp2_i => inp2,
                out_o  => out1
            );
    end generate dummy_g;
end architecture;

正确写法说明 #

针对Generate语句内部实例的嵌入式配置，需要将配置语句放在Generate块的局部声明区（即Generate标签和begin关键字之间），而不是外层架构的声明区。因为Generate块有自己的作用域，外层架构无法直接引用块内的实例标识符。

修正后的代码如下：

library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
    port (
        inp1_i, inp2_i : in std_logic;
        out_o  : out std_logic
    );
end entity;
architecture rtl of and_gate is
begin
    out_o <= inp1_i and inp2_i;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
entity embedded_conf is
end entity embedded_conf;
library work;
architecture struct of embedded_conf is
    signal inp1, inp2, out1  : std_logic;
    component and_gate is
        port (
            inp1_i : in  std_logic;
            inp2_i : in  std_logic;
            out_o  : out std_logic
        );
    end component;
begin
    dummy_g: if true generate
        -- 将配置语句移到Generate块的声明区
        for and_gate_inst : and_gate use entity work.and_gate(rtl);
        and_gate_inst : and_gate
            port map (
                inp1_i => inp1,
                inp2_i => inp2,
                out_o  => out1
            );
    end generate dummy_g;
end architecture;

关键修改点 #

• 移除了架构声明区中错误的嵌套配置语句for dummy_g for ...
• 将针对and_gate_inst的配置语句放在dummy_g Generate块的begin之前，属于该块的局部声明

内容的提问来源于stack exchange，提问作者Matthias Schweikart