Vivado实现Basys板时出现DRC MDRV-1多驱动网错误求助

错误信息 #

[DRC MDRV-1] Multiple Driver Nets: Net ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/nextS[1] has multiple drivers: ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/Q_i_3/O, and ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/Q_i_2/O。

相关代码 #

顶层VHDL代码 #

architecture Structural of xxxxxxxxxxx is

    component WordTo4DigitDisplayDriver is
    port (
            WORD    : in  STD_LOGIC_VECTOR(15 downto 0);
            PULSE   : in  STD_LOGIC;
            CLK     : in  STD_LOGIC;
            SEGMENT : out STD_LOGIC_VECTOR(0 to 6);
            ANODE   : out STD_LOGIC_VECTOR(3 downto 0)
        );
    end component;

    component PulseGenerator_1ms is
        port (
            CLK    : in  STD_LOGIC;
            PULSE  : out STD_LOGIC
        );
    end component;
   
    signal pulse_1ms : STD_LOGIC;

    component ScrollFSM is
        port (
            L       : in  STD_LOGIC;
            R       : in  STD_LOGIC;
            CLK     : in  STD_LOGIC;
            RESET   : in  STD_LOGIC;
            DISPLAY : out STD_LOGIC_VECTOR(1 downto 0)
        );
    end component;
   
begin

    Wt4DDD: WordTo4DigitDisplayDriver
    port map (
        WORD    => SWITCH(15 downto 0),
        PULSE   => pulse_1ms,
        CLK     => CLK,
        SEGMENT => SEGMENT,
        ANODE   => ANODE
    );

    PulseGen: PulseGenerator_1ms
    port map (
        CLK   => CLK,
        PULSE => pulse_1ms
    );
   
    ScrlFSM: ScrollFSM
    port map (
        L       => BTNL,
        R       => BTNR,
        CLK     => CLK,
        RESET   => BTND,
        DISPLAY (1 downto 0) => LED(15 downto 14)
    );

end architecture;

ScrollFSM模块代码 #

architecture Structural of ScrollFSM is

    component Reg_LOAD_CLR_2bit is
        port (
            D    : in  STD_LOGIC_VECTOR(1 downto 0);
            CLK  : in  STD_LOGIC;
            LOAD : in  STD_LOGIC;
            CLR  : in  STD_LOGIC;
            Q    : out STD_LOGIC_VECTOR(1 downto 0)
        );
    end component;
   
    signal currentS : STD_LOGIC_VECTOR(1 downto 0);
    signal nextS    : STD_LOGIC_VECTOR(1 downto 0);
   
    alias NS1 : STD_LOGIC is nextS(1);
    alias NS0 : STD_LOGIC is nextS(0);
    alias S1  : STD_LOGIC is currentS(1);
    alias S0  : STD_LOGIC is currentS(0);

begin

    NS1 <= (not S1 and not S0 and L) or (S1 and S0 and L) or (not S1 and S0 and R) or (S1 and not L and not R) or (S1 and not S0 and not L and not R);
   
    NS1 <= (S0 and not L and not R) or (not S0 and L and not R) or (not S0 and not L and R);
   
    RLC2B: Reg_LOAD_CLR_2bit
    port map (
        D => nextS,
        CLK => CLK,
        LOAD => '1',
        CLR => RESET,
        Q => currentS
    );

    DISPLAY <= currentS;
end architecture;

DFF1模块代码 #

architecture Behavioral of DFF is

begin

    process (CLK)
    begin
        if rising_edge(CLK) then
            Q <= D;
        end if;
    end process;

end architecture;

错误原因分析 #

问题出在ScrollFSM模块中：你对NS1（即nextS[1]）写了两次并行连续赋值语句。在VHDL里，并行赋值是同时生效的，这就相当于给同一个信号接了两个驱动源，直接触发了DRC的多重驱动检测错误。

解决方案 #

1. 先梳理状态转移逻辑，确定两条NS1赋值语句中哪一条是正确的，保留正确的那条，删掉重复的错误赋值。
2. 如果两条语句都是状态转移逻辑的一部分，需要把它们合并成一个逻辑表达式，比如：

NS1 <= ((not S1 and not S0 and L) or (S1 and S0 and L) or (not S1 and S0 and R) or (S1 and not L and not R) or (S1 and not S0 and not L and not R)) 
       OR 
       ((S0 and not L and not R) or (not S0 and L and not R) or (not S0 and not L and R));

建议先画状态转移真值表验证逻辑正确性，再合并表达式，避免引入新的逻辑错误。
3. 修改完成后重新综合实现，就能消除这个DRC错误。

内容的提问来源于stack exchange，提问作者user24647578