VSCode中编译Verilog生成.vvp文件失败，请求技术帮助

尝试将Verilog的.v文件编译为.vvp文件时，在VSCode终端执行编译命令后无任何反应，也没有错误提示。已经检查过文件目录、Icarus Verilog的安装情况及环境变量路径，重装过Icarus Verilog和VSCode相关扩展，更换过代码后问题仍未解决。

与门模块代码 #

//modulo and_gate

module and_gate (input A, input B, output Y);
    assign Y = A & B;
endmodule

测试台代码 #

//Testbench do modulo and_gate
`include "and_gate.v"
module and_gate_tb;
    reg A;
    reg B;
    wire Y;

    // Instancia o módulo and_gate
    and_gate uut (
        .A(A),
        .B(B),
        .Y(Y)
    );

    initial begin
        // Simulação de diferentes casos de teste
        A = 0; B = 0; #10;
        A = 0; B = 1; #10;
        A = 1; B = 0; #10;
        A = 1; B = 1; #10;
        $stop; // Para a simulação
    end
endmodule

执行的终端命令 #

PS C:\iverilog\bin\Teste\ws-verilog\Projeto1> iverilog -o and_gate_tb.vvp and_gate_tb.v

内容的提问来源于stack exchange，提问作者pedro henrique