编译MEN A25 PCIe-VME桥接门电路时遇UTF-8解码错误求助

项目背景 #

我要构建MEN A25 SBC PCIe-VME Bridge Gateware项目，官方给出的FPGA比特流生成步骤如下：

• 执行git submodule update --init获取所有Git子模块
• 确保HDLmake版本高于3.3（至少包含提交3ac2e4e，也可直接使用master分支最新版）
• 安装Altera Quartus 16.0及Cyclone IV GX FPGA系列支持组件
• 进入hdl/syn目录运行hdlmake（需提前将Altera Quartus二进制文件加入系统路径）
• 可选操作：运行make生成比特流，或make project生成Quartus项目后用GUI编译
• 成功后，hdl/syn/fpga_files目录会生成16A025-00_MM_mm文件，仅用该文件烧录FPGA；hdl/syn/A25_top.bin因缺失比特流头不可用

操作过程及输出 #

[gms@localhost ~]$ su
Password: 
[root@localhost gms]# cd VME_test
[root@localhost VME_test]# git clone https://ohwr.org/project/vme-sbc-a25-pcie-vme-bridge.git
Cloning into 'vme-sbc-a25-pcie-vme-bridge'...
remote: Enumerating objects: 821, done.
remote: Counting objects: 100% (216/216), done.
remote: Compressing objects: 100% (168/168), done.
remote: Total 821 (delta 101), reused 48 (delta 48), pack-reused 605
Receiving objects: 100% (821/821), 7.90 MiB | 1.59 MiB/s, done.
Resolving deltas: 100% (381/381), done.
[root@localhost VME_test]# cd hdl/syn
[root@localhost syn]# git submodule init
Submodule 'general-cores' (https://ohwr.org/project/general-cores.git) registered for path '../../dependencies/general-cores'
Submodule 'vme-bridge' (https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/vme-bridge.git) registered for path '../../dependencies/vme-bridge'
[root@localhost syn]# git submodule update
Cloning into '/home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/dependencies/general-cores'...
Cloning into '/home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/dependencies/vme-bridge'...
Submodule path '../../dependencies/general-cores': checked out '3c636a53f7c6605fbb8c66093a3dcb08132a572c'
Submodule path '../../dependencies/vme-bridge': checked out 'e529102a1c05540a68588ebd74f8dd8e9ff4722a'
[root@localhost syn]# hdlmake fetch
INFO    <string>:14: <module>() Library component wb_fine_pulse_gen targets only xilinx devices
INFO    <string>:11: <module>() Library component wb_xc7_fw_update targets only xilinx devices
INFO    commands.py:120: fetch()    Fetching needed modules.
INFO    commands.py:130: fetch()    All modules fetched.
[root@localhost syn]# hdlmake
INFO    <string>:14: <module>() Library component wb_fine_pulse_gen targets only xilinx devices
INFO    <string>:11: <module>() Library component wb_xc7_fw_update targets only xilinx devices
INFO    action.py:139: build_file_set() Detected 2 supported files that are not parseable
INFO    action.py:141: build_file_set() not parseable: /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/hdl/syn/A25_top.sdc
INFO    action.py:141: build_file_set() not parseable: /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/hdl/16z091-01_src/Synthesis/z91_01_tmg_con.sdc
INFO    action.py:144: build_file_set() Detected 252 supported files that can be parsed
ERROR   main.py:71: hdlmake()   'utf-8' codec can't decode byte 0xfc in position 2405: invalid start byte
[root@localhost syn]# export PATH=$PATH:/home/intelFPGA/17.0/quartus/bin/
[root@localhost syn]# hdlmake
INFO    <string>:14: <module>() Library component wb_fine_pulse_gen targets only xilinx devices
INFO    <string>:11: <module>() Library component wb_xc7_fw_update targets only xilinx devices
INFO    action.py:139: build_file_set() Detected 2 supported files that are not parseable
INFO    action.py:141: build_file_set() not parseable: /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/hdl/16z091-01_src/Synthesis/z91_01_tmg_con.sdc
INFO    action.py:141: build_file_set() not parseable: /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/hdl/syn/A25_top.sdc
INFO    action.py:144: build_file_set() Detected 252 supported files that can be parsed
ERROR   main.py:71: hdlmake()   'utf-8' codec can't decode byte 0x96 in position 1906: invalid start byte

当前环境信息 #

• Quartus版本：17.0
• HDLmake版本：3.3（安装输出如下）

[root@localhost hdl-make]# python3.6 setup.py install
hdlmake 3.3 is already the active version in easy-install.pth
Installing hdlmake script to /usr/local/bin

Installed /usr/local/lib/python3.6/site-packages/hdlmake-3.3-py3.6.egg
Processing dependencies for hdlmake==3.3
Finished processing dependencies for hdlmake==3.3

解决方案 #

1. 升级HDLmake到符合要求的版本 #

官方要求HDLmake版本需高于3.3且包含提交3ac2e4e，当前3.3版本不满足要求，直接安装master分支最新版：

# 卸载现有版本
pip uninstall hdlmake
# 克隆最新源码并安装
git clone https://ohwr.org/project/hdlmake.git
cd hdlmake
python3.6 setup.py install

2. 修复项目文件编码问题 #

解码错误说明项目中存在非UTF-8编码的文件，可通过以下方式处理：

• 定位错误提示中提到的文件位置，用文本编辑器打开后另存为UTF-8编码（比如0xfc对应德语ü，0x96对应特殊破折号，这类字符常出现在ISO-8859-1编码文件中）；
• 用命令行批量转换项目中的HDL/约束文件编码：

# 备份项目文件（可选但建议）
cp -r /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge_backup
# 批量转换为UTF-8编码
find /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge -type f \( -name "*.v" -o -name "*.sv" -o -name "*.sdc" \) -exec iconv -f ISO-8859-1 -t UTF-8 {} -o {} \;

3. 临时绕过编码检查（不推荐，仅作为应急方案） #

如果升级HDLmake和转码后仍有问题，可修改HDLmake源码，在读取文件时指定兼容编码：
找到main.py中读取文件的代码段，将open(file_path, 'r')改为open(file_path, 'r', encoding='latin-1')，该编码可兼容大部分非UTF-8字符。

内容的提问来源于stack exchange，提问作者chami