ISE综合报告缺失完整Timing Report（含延迟信息）求助

我编写了一个行缓冲寄存器组代码，在ISE软件中综合后，无法获取完整的Timing Report，尤其是设计的延迟信息。推测该问题由大量编译警告导致，代码如下：

module Buffer
# (parameter COUNT= 253)//   Size of Line Buffer 
  (
    input clk,rst,
    input [7:0]Pixel,
    output reg [7:0] R1,R2,R3,R4,R5,R6,R7,R8,R9
    );
    
    reg [7:0] line_buff1 [COUNT-1:0];
    reg [7:0] line_buff2 [COUNT-1:0];
    reg [7:0] RT1,RT2,RT3,RT4,RT5,RT6,RT7,RT8,RT9;// Temporary  Registers
    integer i;
    
    always @ (posedge clk)
    begin
    if(rst) begin
    RT7 <= 1'd0;
    RT8 <= 1'd0;
    RT9 <= 1'd0;
    RT4 <= 1'd0;
    RT5 <= 1'd0;
    RT6 <= 1'd0;
    RT1 <= 1'd0;
    RT2 <= 1'd0;
    RT3 <= 1'd0;
    end
    
    else begin
    
    RT9 <= Pixel;
    RT8 <= RT9;
    RT7 <= RT8;
    line_buff2[0] <= RT7;
    RT6 <= line_buff2[COUNT-1];
    
    for ( i=COUNT-2 ; i>=0; i=i-1 )
        line_buff2[i+1] <= line_buff2[i];
 
 
     RT5 <= RT6;
     RT4 <= RT5;
     line_buff1[0] <= RT4;
     RT3 <= line_buff1[COUNT-1];
     
     for ( i=COUNT-2 ; i>=0; i=i-1 )
         line_buff1[i+1] <= line_buff1[i];
   RT2 <= RT3;
   RT1 <= RT2;
   end
   end
   
   
   
   always @(*)
   if(RT1 !== 8'bx)  begin
   R1<=RT1;
   R2<=RT2;
   R3<=RT3;
   R4<=RT4;
   R5<=RT5;
   R6<=RT6;
   R7<=RT7;
   R8<=RT8;
   R9<=RT9;
   end 
   
  endmodule

代码问题分析与修正 #

1. 组合逻辑误用非阻塞赋值 #

第二个always @(*)块属于组合逻辑，却使用了时序逻辑的非阻塞赋值（<=），这会触发工具警告，甚至意外生成锁存器。需改为阻塞赋值（=），并补全else分支避免锁存器。

2. 复位不完整 #

仅复位了临时寄存器RT1-RT9，未复位line_buff1和line_buff2数组，工具会报未复位寄存器警告，影响时序分析完整性。

3. 移位赋值位宽不匹配 #

复位时用1'd0赋值8位寄存器，存在位宽不匹配警告，需统一改为8'd0。

修正后代码 #

module Buffer
# (parameter COUNT= 253)//   Size of Line Buffer 
  (
    input clk,rst,
    input [7:0]Pixel,
    output reg [7:0] R1,R2,R3,R4,R5,R6,R7,R8,R9
    );
    
    reg [7:0] line_buff1 [COUNT-1:0];
    reg [7:0] line_buff2 [COUNT-1:0];
    reg [7:0] RT1,RT2,RT3,RT4,RT5,RT6,RT7,RT8,RT9;// Temporary  Registers
    integer i;
    
    always @ (posedge clk)
    begin
        if(rst) begin
            // 复位所有临时寄存器（统一位宽）
            RT1 <= 8'd0;
            RT2 <= 8'd0;
            RT3 <= 8'd0;
            RT4 <= 8'd0;
            RT5 <= 8'd0;
            RT6 <= 8'd0;
            RT7 <= 8'd0;
            RT8 <= 8'd0;
            RT9 <= 8'd0;
            // 复位两个行缓冲数组
            for (i = 0; i < COUNT; i = i + 1) begin
                line_buff1[i] <= 8'd0;
                line_buff2[i] <= 8'd0;
            end
        end
        else begin
            // 移位链更新
            RT9 <= Pixel;
            RT8 <= RT9;
            RT7 <= RT8;
            
            // line_buff2移位
            line_buff2[0] <= RT7;
            for (i = COUNT-2; i >= 0; i = i - 1) begin
                line_buff2[i+1] <= line_buff2[i];
            end
            RT6 <= line_buff2[COUNT-1];
            
            RT5 <= RT6;
            RT4 <= RT5;
            
            // line_buff1移位
            line_buff1[0] <= RT4;
            for (i = COUNT-2; i >= 0; i = i - 1) begin
                line_buff1[i+1] <= line_buff1[i];
            end
            RT3 <= line_buff1[COUNT-1];
            
            RT2 <= RT3;
            RT1 <= RT2;
        end
    end
   
    // 组合逻辑使用阻塞赋值，补全else分支避免锁存器
    always @(*) begin
        if(RT1 !== 8'bx) begin
            R1 = RT1;
            R2 = RT2;
            R3 = RT3;
            R4 = RT4;
            R5 = RT5;
            R6 = RT6;
            R7 = RT7;
            R8 = RT8;
            R9 = RT9;
        end else begin
            R1 = 8'd0;
            R2 = 8'd0;
            R3 = 8'd0;
            R4 = 8'd0;
            R5 = 8'd0;
            R6 = 8'd0;
            R7 = 8'd0;
            R8 = 8'd0;
            R9 = 8'd0;
        end
    end 
   
endmodule

生成完整时序报告步骤 #

1. 消除所有警告：使用修正后的代码重新综合，确保无编译警告。
2. 开启时序分析选项：
   • 在ISE的Project Navigator中，右键点击Synthesize - XST，选择Process Properties。
   • 切换到Timing Constraints标签，勾选Enable Timing Analysis，并设置对应时钟周期约束（例如输入时钟的实际周期）。
3. 生成时序报告：重新运行综合后，可在综合报告中查看延迟信息；也可右键点击Synthesize - XST，选择Generate Post-Synthesis Timing Report获取详细时序分析结果。

内容的提问来源于stack exchange，提问作者Fraser