VHDL编译报错：无法将universal_integer转换为MemoryArray类型

错误信息 #

Error (10305): VHDL Type Conversion error at registers.vhd(28): cannot convert type "universal_integer" to type "MemoryArray"

问题代码 #

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity registers is
    port(   load : in std_logic;                                    -- 1-bit input
            WriteAddr : in std_logic_vector(1 downto 0);    -- 2 bit write address
            Memin : in std_logic_vector(5 downto 0);    -- 6 bit input data
            clk : in std_logic;                 -- clock
            Memout : out std_logic_vector(5 downto 0)); -- 6 bit output data
end registers;

architecture arch of registers is
    type MemoryArray is array(0 to 3) of STD_LOGIC_VECTOR(5 downto 0); --array of size 4, each index holds 6 bit values
    signal Memory : MemoryArray := (others => (others => '0'));

begin
    
    process(clk)
    begin
        if rising_edge(clk) then
            if (load = '1') then
                case WriteAddr is
                    
                    when "00" =>
                        MemoryArray(0) <= Memin;
                    when "01" =>
                        MemoryArray(1) <= Memin;
                    when "10" =>
                        MemoryArray(2) <= Memin;
                    when "11" =>
                        MemoryArray(3) <= Memin;
                end case;   
            end if;
        end if;
    end process;
    
    process(WriteAddr)
    begin
                     
        case WriteAddr is
            
            when "00" =>
                Memout <= Memory(0);
                
            when "01" =>
                Memout <= Memory(1);
                
            when "10" => 
                Memout <= Memory(2);
                
            when others =>
                Memout <= Memory(3);
        end case;
        
    end process;
    
end arch;

错误原因与修正 #

错误核心是误将**类型名MemoryArray**当作信号来赋值。MemoryArray是你定义的数组类型，实际存储数据的是你声明的信号Memory。

基础修正方案 #

把第一个进程里的MemoryArray(0)、MemoryArray(1)等全部替换为Memory(0)、Memory(1)即可：

process(clk)
begin
    if rising_edge(clk) then
        if (load = '1') then
            case WriteAddr is
                
                when "00" =>
                    Memory(0) <= Memin;
                when "01" =>
                    Memory(1) <= Memin;
                when "10" =>
                    Memory(2) <= Memin;
                when "11" =>
                    Memory(3) <= Memin;
            end case;   
        end if;
    end if;
end process;

代码优化方案 #

可以去掉冗长的case语句，直接将WriteAddr转换为整数索引，让代码更简洁：

process(clk)
begin
    if rising_edge(clk) then
        if load = '1' then
            Memory(to_integer(unsigned(WriteAddr))) <= Memin;
        end if;
    end if;
end process;

内容的提问来源于stack exchange，提问作者Zachary Adolphsen