Intel FPGA ModelSim报错：无效时间字符串问题求助

问题分析 #

台式机使用Quartus Prime Lite搭配ModelSim仿真时，出现Invalid time string specified错误，编译环节无异常但仿真启动失败。相同代码与脚本在笔记本可正常运行，问题出现于通过GitHub传输文件之后，核心诱因大概率是脚本语法解析异常或文件换行符/编码不兼容。

解决方案 #

1. 修复仿真脚本的引号语法错误 #

从编译日志可见，vsim命令被解析为：

vsim -voptargs=""+acc"" -t 1ps -lib work mux2_1_tb

嵌套双引号导致-voptargs参数解析混乱，进而触发时间字符串错误。修改仿真脚本中的vsim行：

# 原错误行
vsim -voptargs="+acc" -t 1ps -lib work mux2_1_tb

# 修改为（移除多余引号）
vsim -voptargs=+acc -t 1ps -lib work mux2_1_tb

2. 统一文件换行符为Windows格式 #

GitHub默认会自动转换换行符（Windows为CRLF，类Unix为LF），ModelSim对换行符敏感，尤其是.do脚本文件：

• 用Notepad++等编辑器打开所有.do文件（runlab.do、mux2_1_wave.do）
• 切换换行符格式为「Windows (CRLF)」，保存后重新运行仿真
• 若需避免Git自动转换，在仓库执行：

  git config core.autocrlf false
  

3. 排查波形文件异常 #

错误指向时间字符串，需检查mux2_1_wave.do是否存在非法时间配置：

• 打开文件查看是否有类似-time参数的错误设置（如格式错误、空值）
• 暂时注释仿真脚本中的do mux2_1_wave.do行，重新运行仿真，若不再报错则说明波形文件存在问题，需重构或修复该文件

4. 验证ModelSim环境配置 #

确保台式机的ModelSim安装路径无中文、空格等特殊字符，系统PATH环境变量正确包含ModelSim的二进制目录（如C:/intelFPGA_lite/17.0/modelsim_ase/win32aloem）。

原始问题相关文件 #

编译日志 #

Reading C:/intelFPGA_lite/17.0/modelsim_ase/tcl/vsim/pref.tcl
do runlab.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 22:33:47 on Apr 12,2025
# vlog -reportprogress 300 ./mux2_1.sv 
# -- Compiling module mux2_1
# 
# Top level modules:
#   mux2_1
# End time: 22:33:47 on Apr 12,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 22:33:47 on Apr 12,2025
# vlog -reportprogress 300 ./mux2_1_tb.sv 
# -- Compiling module mux2_1_tb
# 
# Top level modules:
#   mux2_1_tb
# End time: 22:33:47 on Apr 12,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -voptargs=""+acc"" -t 1ps -lib work mux2_1_tb 
# Start time: 22:33:47 on Apr 12,2025
# Loading sv_std.std
# Loading work.mux2_1_tb
# Loading work.mux2_1
# Invalid time string specified: 

模块代码（mux2_1.sv） #

// Implementation of a 2:1 multiplexor
// The output will match the corresponding input (i0 or i1) based on
// the value of the selector bit (sel).
module mux2_1 (
  output logic out
  ,input  logic i0, i1, sel
  );

  assign out = (i1 & sel) | (i0 & ~sel);
endmodule  // mux2_1

测试代码（mux2_1_tb.sv） #

// Testbench for the mux2_1 module
// Runs through all 8 combinations of inputs, changing every 10 time units.
module mux2_1_tb();
  logic out;
  logic i0, i1, sel;

  // instantiate device under test (dut)
  mux2_1 dut (.out, .i0, .i1, .sel);

  // test input sequence
  initial begin
    sel=0; i0=0; i1=0; #10;
    sel=0; i0=0; i1=1; #10;
    sel=0; i0=1; i1=0; #10;
    sel=0; i0=1; i1=1; #10;
    sel=1; i0=0; i1=0; #10;
    sel=1; i0=0; i1=1; #10;
    sel=1; i0=1; i1=0; #10;
    sel=1; i0=1; i1=1; #10;
    $stop;  // needed to pause the simulation without closing it
  end
endmodule  // mux2_1_tb

仿真脚本（runlab.do） #

# Create work library
vlib work

# Compile Verilog
#     All Verilog files that are part of this design should have
#     their own "vlog" line below.
vlog "./mux2_1.sv"
vlog "./mux2_1_tb.sv"

# Call vsim to invoke simulator
#     Make sure the last item on the line is the name of the
#     testbench module you want to execute.
vsim -voptargs="+acc" -t 1ps -lib work mux2_1_tb

# Source the wave do file
#     This should be the file that sets up the signal window for
#     the module you are testing.
do mux2_1_wave.do

# Set the window types
view wave
view structure
view signals

# Run the simulation
run -all

# End

内容的提问来源于stack exchange，提问作者youlexa